Exynos 5 Dual

General Description

The Exynos 5 Dual SoC is based on the 32-bit RISC processor for mobile devices such as smartphones, tablets and netbooks. Designed using 32-nm low-power process, the Exynos 5 Dual provides the best performance and broadest feature set, such as a Cortex-A15 dual core CPU, the widest memory bandwidth available in-class, WQXGA display (2560x1600), 1080p 60 fps video encoding and decoding hardware, 3D graphics hardware, an image signal processor, and high-speed interfaces, such as eMMC 4.5, USB 3.0 and SATA3.
Specifications

ARM Core Series Cortex A15
Production Status Customer Sample
Speed 1.7GHz/2.0GHz(TBD)
Features Dual core, LPDDR2/LPDDR3/DDR3 Dual channel memory, WQXGA 60fps 3D graphic support, 32nm HKMG process, 1080p 60fps multi format codec, 8Mpix 30fps Embedded ISP
Package SCP: 1088FCFBGA. POP: 1036FCFBGA
Detail Features
CortexA15 dual core subsystem with 64-/128-bit SIMD NEON
32KB (Instruction)/32KB (Data) L1 Cache and 1MB L2 Cache
128-bit Multi-layered bus architecture
Internal ROM and RAM for secure booting, security, and general purposes
Memory Subsystem
- 2-ports 32-bit 800MHz LPDDR3/DDR3 Interfaces
- 2-ports 32-bit 533MHz LPDDR2 Interfaces
8-bit ITU 601 Camera Interface
Multi-format Video Hardware Codec: 1080p 60fps (capable of decoding and encoding MPEG-4/H.263/H.264 and decoding only MPEG-2/VC1/VP8)
3D and 2D graphics hardware, supporting OpenGL ES 1.1/2.0/Halti, OpenVG 1.1 and OpenCL 1.1 full profile
Image Signal Processor : supporting BayerRGB up to 14bit input with 14.6MP 15fps, 8MP 30fps through MIPI CSI2 & YUV 8bit interfaces and special functionalities such as 3-dimensional noise reduction (3DNR), video digital image stabilization (VDIS) and optical distortion compensation (ODC)
JPEG Hardware Codec
LCD single display, supporting max WQXGA, 24bpp RGB, YUV formats through MIPI DSI or eDP
Simultaneously display of WQXGA single LCD display and 1080p HDMI
HDMI 1.4 interfaces with on-chip PHY
2-ports (4-lanes) MIPI CSI2 interfaces
1-port (4-lanes) eDisplayPort (eDP)
1-channel USB 3.0 Device or Host, supporting SS (5Gbps) with on-chip PHY
1-channel USB 2.0 Host or Device, supporting LS/FS/HS (1.5Mbps/12Mbps/480Mbps) with on-chip PHY
2-channel USB HSIC, supporting 480Mbps with on-chip PHY
1-channel HS-MMC 4.5
1-channel SDIO 3.0
2-channel SD 2.0 or HS-MMC4.41
4-channel high-speed UART (up to 3Mbps data rate for Bluetooth 2.1 EDR and IrDA 1.0 SIR)
3-channel SPI
1-channel AC-97, 2-channel PCM, and 3-channel 24-bit I2S audio interface, supporting 5.1 channel audio
1-channel S/PDIF interface support for digital audio
4-channel I2C interface support (up to 400kbps) for PMIC, HDMI, and general-purpose multi-master
4-channel HS-I2C (up to 3.1 Mbps)
Samsung Reconfiguration Processor supports low power audio play
MIPI-HSI v1.1, supporting 200Mbps full-duplex
C2C, supporting through path between DRAM and MODEM
Security subsystem supporting hardware crypto accelerators, ARM TrustZone and TZASC
32-channel DMA Controller
Configurable GPIOs
Real time clock, PLLs, timer with PWM, multi-core timer, and watchdog timer